AT=1CYCLE, RES=12BIT, REF=1V25
Single Channel Control Register
| REP | Single Channel Repetitive Mode |
| DIFF | Single Channel Differential Mode |
| ADJ | Single Channel Result Adjustment |
| RES | Single Channel Resolution Select 0 (12BIT): 12-bit resolution. 1 (8BIT): 8-bit resolution. 2 (6BIT): 6-bit resolution. 3 (OVS): Oversampling enabled. Oversampling rate is set in OVSRSEL. |
| REF | Single Channel Reference Selection 0 (1V25): VFS = 1.25V with internal VBGR reference 1 (2V5): VFS = 2.5V with internal VBGR reference 2 (VDD): VFS = AVDD with AVDD as reference source 3 (5V): VFS = 5V with internal VBGR reference 4 (EXTSINGLE): Single ended external reference 5 (2XEXTDIFF): Differential external reference, 2x 6 (2XVDD): VFS = 2xAVDD with AVDD as the reference source 7 (CONF): Use SINGLECTRLX to configure reference |
| POSSEL | Single Channel Positive Input Selection |
| NEGSEL | Single Channel Negative Input Selection |
| AT | Single Channel Acquisition Time 0 (1CYCLE): 1 conversion clock cycle acquisition time for single channel 1 (2CYCLES): 2 conversion clock cycles acquisition time for single channel 2 (3CYCLES): 3 conversion clock cycles acquisition time for single channel 3 (4CYCLES): 4 conversion clock cycles acquisition time for single channel 4 (8CYCLES): 8 conversion clock cycles acquisition time for single channel 5 (16CYCLES): 16 conversion clock cycles acquisition time for single channel 6 (32CYCLES): 32 conversion clock cycles acquisition time for single channel 7 (64CYCLES): 64 conversion clock cycles acquisition time for single channel 8 (128CYCLES): 128 conversion clock cycles acquisition time for single channel 9 (256CYCLES): 256 conversion clock cycles acquisition time for single channel |
| PRSEN | Single Channel PRS Trigger Enable |
| CMPEN | Compare Logic Enable for Single Channel |